Intel & AMD Micro-Architecture Extended Instruction Sets

The following is a list of architectures where certain instruction sets have been introduced first. The column "instr. set" only lists the introduced, not all instruction sets.


Only includes consumer CPUs, not Xeons or other prosumer hardware.

Year uArch instr. set
2007 Intel Core SSE, SSE2, SSE3, SSSE3, SSE4
2007 Penryn SSE4.1, VT-x, VT-d
2008 Nehalem SSE4.2
2010 Westmere AES-NI, CLMUL
2011 Sandy Bridge AVX, TXT
2012 Ivy Bridge F16C
2013 Haswell FMA3, AVX2, TSX (only Haswell-EX)
2015 Skylake MPX, SGX, HEVC
2016 Kaby Lake -
2017 Coffee Lake -
2018 Cannon Lake AVX-512, SHA
2018 Cascade Lake TBD
2018 Whiskey Lake TBD
2019 Ice Lake TBD


Year uArch instr. set
2003 Hammer (K8) SSE, SSE2 (SSE3, starting with Athlon64)
2007 K10 AMD-V, SSE4a
2011 Bobcat (K14) ABM
2011 Bulldozer (K15) SSSE3, SSE4.1, SSE4.2, AES, CLMUL, AVX, XOP, FMA4, F16C
2012 Piledriver (K15) FMA3
2012 Steamroller (K15) HEVC
2013 Jaguar (K16) MOVBE
2017 Zen (K17) AVX2, SHA, ADX, RDSEE

If you see any errors, please contact me on Twitter @ArvidGerstmann.